Process for electropolishing both sides of a semiconductor simultaneously



Dec. 20, 1966 M. v. SULLIVAN 3,293,152 PROCESS FOR ELECTROPOLISHING BOTH SIDES OF A SEMICONDUCTOR SIMULTANEOUSLY Filed June 30, 1964 2 Sheets-Sheet 1 E2 mu:

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W 3 H O N S INVENTOR By M. l SULLIVAN fw/ kink ATTORNEY Dec. 20, 1966 M. v. SULLIVAN 3,293,162

PROCESS FOR ELECTROPQLISHING BOTH SIDES OF A SEMICONDUCTOR SIMULTANEOUSLY Filed June 50, 1964 2 Sheets-Sheet 2 United States Patent PROCESS FOR ELECTROPOLISHING BOTH SlDES OF A SEMICONDUCTOR SllVlULTANEOUSLY Miles V. Sullivan, Summit, N.J., assignor to Bell Telephone Laboratories, Incorporated, New York, N.Y., a

corporation of New York Filed June 30, 1964, Ser. No. 379,163 3 Claims. (Cl. 204-1405) This invention relates to a technique for electropolishing. More particularly, the present invention relates to a technique for electropolishing semiconductor surfaces.

Recently, a technique for electropolishing semiconductor surfaces was described in US. Patent 3,073,764, issued January 15, 1963, wherein such surfaces were attained Within very exacting tolerances in flatness, smoothness and damage. The inventive procedure described therein involved mounting a plated and waxed material to be polished on a rotatable disk such that the surface of interest is exposed, a second rotatable disk covered by a suitable low pile cloth being positioned proximate the surface of interest such that the pile of the cloth is barely in contact with such surface. Thereafter, a selected electrolyte is provided to a level above the pile of the cloth for contacting the surface of interest and the second disk is rotated about an axis of rotation parallel to but displaced laterally from that about which the first disk is rotated. Surfaces treated in accordance with this technique evidence smoothness of at least 0.2 microinch, flatness of at least 0.0001 inch and are free of mechanical damage.

Although the described technique has been entirely satisfactory, the trend toward the use of thinner-semiconductor sections in device technology has necessitated the development of a technique for applying the same type of intensive stirring (as described above) to both faces of a semiconductor slice simultaneously, thereby reducing internal stresses which are commonly present when one face is lapped with a moderately coarse abrasive and the other is highly polished,

In accordance with the present invention, this end is attained by suspending a semiconductor wafer in an electrolyte between two closely spaced flat electrodes, applying an alternating current across the electrodes and rotating the wafer in a plane substantially parallel to the electrodes. The inventive procedure results in a stress free wafer which is free of dimpling and is economically attractive in that several operations normally performed are eliminated, for example, plating, waxing, deplating and dewaxing.

The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawing wherein:

FIG. 1 is a front elevational view, partly in section, of an exemplary apparatus used in the practice of the present invention;

FIG. 1A is an exploded schematic diagram of the apparatus shown in FIG. 1; and

FIG. 2 is a profile pattern of a germanium wafer polished in accordance with the present invention.

With reference now more particularly to FIG. 1, there is shown a front elevational view, partly in section, of a planetary lapping machine adapted for use in the practice of the present invention. Shown in the figure is a cylindrical container 11, including a rotating mechanism 12, typically an electric motor, which transmits angular motion to gears 13 and 14 by means of shaft 15. Gear 13 meshes with gear 16 which, in turn, is connected to gear 17 by means of shaft 18, gear 17 meshing with gear 19. Electrodes 20 and 21 connected to a source of alternating current, not shown, are positioned upon platform Fee 22, the electrodes faces being covered by low pile cloths 23 and 24, respectively. Sample nests 25 and 26 containing samples 27 and 28, respectively, are positioned intermediate electrodes 20 and 21, the sample nests being in the shape of a gear and meshing with gear 14. A source of electrolyte 29 provides the electrolyte during the polishing process by means of conduit 30 controlled by valve 31.

In the operation of the polishing process at least one semiconductor slice is inserted in sample nest 25 or 26 such that the surfaces thereof are in contact with the pile of low pile cloths or papers 23 and 24. Typically, low pile cloths or papers 23 and 24 are materials such as Pellon, Dextilose, nylon, etc., which are obtained from commercial sources. The term low pile as employed herein refers to any cloth or paper having a pile of height of approximately 0.020 inch or less. The next step in the processing procedure involves admitting a suitable electrolyte in a continuous supply into the apparatus, the level thereof being maintained sufliciently high as to Wet the surfaces of interest.

Finally, an alternating potential is applied between electrodes 20 and 21 and motor 12 started, thereby causing the angular movement of gears 13 and 14, gear 13, in turn, actuating gear 16, which transmits angular motion to gear 17 by means of shaft 18, and gear 19. The sample nests are actuated by means of gear 14 and electrolyte which is being fed to the upper electrode 20 is carried by the nests 25 and 26 around and between the lapping blocks (electrodes 20 and 21). An exploded schematic diagram of the apparatus of FIG. 1 is shown in FIG. 1A.

The electrolyte selected for use in accordance with the described technique is dependent upon the nature of the material being polished, such being well known to those skilled in the art. For example, a material found particularly useful in the polishing of germanium and silicon is 0.025 percent potassium hydroxide by weight in deionized water.

Voltage requirements in the operation of the process vary with the thickness of the polishing cloths or papers, cloths and papers found particularly useful being within the range of 4 to 8 mils in thickness. However, in general, it has been found advantageous to employ voltages ranging from 10 to 50 volts A.-C., the lower limit being occasioned by unsatisfactory polishing, whereas the upper limit is occasioned by undesirable heating beyond that point. Currents selected for use in the described technique may range from 0.5 to 15 amperes. Frequencies selected may range up to several hundred cycles per second.

The rate of rotation of the sample nests effects the polishing action by influencing the rate of removal of the polishing products, such being necessary in order to prevent their being redeposited during the plating portion of the A.-C. cycle. For the purposes of the present invention, it has been found advantageous to drive the sample nests at speeds ranging from 20 to 900 rpm.

Examples of the present invention are described in detail below. These examples are included merely to aid in the understanding of the invention, and variations may be made by one skilled in the art without departing from the spirit and scope of the invention.

Example I 5 slices of 111) oriented p-type germanium, approximately 0.250 inch x 0.400 inch, lapped with 5 micron abrasive were inserted in 10 mil Mylar sample nests in the apparatus shown in FIG. 1. The apparatus included two electrodes which were covered with finely woven nylon cloths threads per inch) of approximately 4 mils thickness. The electrolyte comprising 0.025 percent KOH by Weight in deionized water was fed to the apparatus at a rate of cc./-min. and electropolisbing initiated at the rate of 0.1 mil per minute with a total current of 2 amperes by applying a potential of 25 volts A.-C. having a frequency of 10 cycles per second across the electrodes (in the form of a square Wave) obtained by reversing the output of a simple D.-C. source through a mechanical relay at a frequency of approximately /2 second, the sample nests being rotated at 500 r.p.m. After removing 3.6 mils of germanium from the total thickness of each slice, the surfaces were fiat Within 0.1 mil and manifested an average surface roughness, as measured on a Brush Surface Analyzer, of 0.2-0.4 microinch. FIG. 2 is a profile pattern of this surface, profilometer measurements being made on a Talysurf model 3.

Example 11 The procedure of Example I was repeated employing germanium slices which had been mechanically polished with Linde A (0.3 micon particle size). The slices, which were flat to within 0.1 mil before electropolishing, were brought to Within 0.02 mil after 2 mils of germanium had been removed. The resultant surfaces evidenced an average roughness of 0.1 microinch.

While the invention has been described in detail in the foregoing specification, and thedrawing similarly illustrates the same, it will be appreciated by those skilled in the art that various modifications may be made Without departing from the spirit and scope of the invention, reference being bad to the appended claims.

What is claimed is:

1. A process for the electropolishing of a semiconductor wafer which comprises the steps of suspending a 4 semiconductor wafer in an electrolyte between two closely spaced fiat electrodes having parallel juxtaposed working faces and having a cloth fixed thereon, said cloth having a pile less then about 0.020 inch, applying an alternating current across said electrodes and rotating the said wafer along a plane substantially parallel to said electrodes, thereby permitting the simultaneous polishing of both faces of said wafer..

2.. A process in accordance With the procedure of claim 1 wherein said semiconductor wafer is rotated at a rate within the range of 20 to 900 rpm.

3. A process in accordance with the procedure of claim 1 wherein said semi-conductor wafer is p-type germanium, said electrolyte is 0.025 percent KOH by weight in deionized water and the total current is 2 amperes.

References Cited by the Examiner UNITED STATES PATENTS 2,294,227 8/ 1942 De Laplace 204140.5 2,539,455 1/1951 Mazia 204-224 2,590,927 4/ 1952 Brandt 204212 2,939,825 4/1960 Faust 204-l42 2,9 65,5 5 6 12/ 1960 Damgaard 204-4405 2,983,65 5 5/ 1961 Sullivan 204143 3,073,764 l/1963 Sullivan 204-140.5

FOREIGN PATENTS 576,351 5/1959 Canada.

JOHN H. MACK, Primary Examiner.

R. MIHALEK, Assistant Examiner, 

1. A PROCESS FOR THE ELECTROPOLISHING OF A SEMICONDUCTOR WAFER WHICH COMPRISES THE STEPS OF SUSPENDING A SEMICONDUCTOR WAFER IN AN ELECTRLYTE BETWEEN TWO CLOSELY SPACED FLAT ELECTRODES HAVING PARALLEL JUXTAPOSED WORKING FACES AND HAVING A CLOTH FIXED THEREON, SAID CLOTH HAVING A PILE LESS THAN ABOUT 0.020 INCH, APPLYING AN ALTERNATING CURRENT ACROSS SAID ELECTRODES AND ROTATING THE SAID WAFER ALONG A PLANE SUBSTANTIALLY PARALLEL TO SAID ELECTRODES, THEREBY PERMITTING THE SIMULTANEOUS POLISHING OF BOTH FACES OF SAID WATER. 